A number of remarks on the correctness of some statements in the "Media and SDR processors literature study" (credits: Bjorn De Sutter):

Section 2.4, under "delay slots": "delay slots are not used since branch prediction isn't use either". Not having delay slots is not the result of not having branch prediction. Both techniques are alternatives (can be used together as well) to hide the latency of conditional branches, i.e. the work around pipeline bubbles that follow from not knowing the outcome of the branch until late in the pipeline. On SDR, in which the scalar path is not wide, nor very deep, nor critical for performance, there is simply no need to hide that latency.

Section 3.3.1, under delay slots: the trimedia has long-latency operations as well, just like the TI. For example, IIRC from my thesis 10 years ago, the multiplication takes 3 cycles in a TriMedia, and during that time, the destination register is still available for other purposes.

Section 4.3 and others: The scalar data paths on the SDR architectures are usually not considered as being VLIW data paths, as they are only one issue slot wide.